The present invention relates to a semiconductor arithmetic circuit, and in particular, provides a highly functional semiconductor integrated circuit which is capable of comparing the magnitudes of a plurality of data at high speeds, and continuously, using hardware.
In the fields of data processing and automatic control, the comparison of data expressed in numbers, and the discrimination of their magnitudes, plays an extremely important role.
Examples of this include the determination of the larger of 2 numbers, the selection of the datum having the largest value from a plurality of inputted data, the arrangement of a plurality of data according to their numerical size, that is to say, sorting, and the like.
Such operations can be accomplished using common calculators; however, because it is necessary to conduct a large number of calculations, time is required and it is extremely difficult to use such methods in real time control. In particular, in the case of the control of robots and the like, it is necessary to attach calculators to the robots to perform the calculations, so that there has been a demand for the realization of such functions using small LSI chips.
When attempts were made to conduct such operations using microprocessors by means of the programming of these microprocessors, an enormous amount of time was required, and practical application was essentially impossible. Research and development have been conducted into the production of circuits which are directly capable of comparing magnitudes by means of the hardware thereof; however, a large number of elements are required to realize such circuitry, and since calculations are conducted via circuitry having a number of stages, the development of small LSI having high speed arithmetical functions has not yet been realized.
The present invention has as an object thereof to provide a semiconductor device which is capable of conducting, in real time, the high speed comparison of the magnitudes of a plurality of data using simple circuitry.
The present invention is a semiconductor arithmetic circuit constituted using one or more neuron MOS, each having: a semiconductor region of one conductivity type on a substrate, a source and drain regions of an opposite conductivity type provided on said semiconductor region, a floating gate electrode provided via an insulating film at a region separating said source and drain regions, which is in an electrically floating state, and a plurality of input gate electrodes capacitively coupled with said floating gate electrode via an insulating film; wherein an inverter circuit group containing a plurality of inverter circuits constituted as neuron MOS transistors is provided, a means is provided for applying a prescribed signal voltage to at least one first input gate of said inverter circuit, the output signals of all the inverters contained in said inverter circuit group, are inputted directly, or through prescribed number of inverters, to a logical operation circuit, and the output signal of said logical operation circuit is fed back directly, or through prescribed number of inverters, to at least one second input gate of each said inverter circuit contained in said inverter circuit group.
Furthermore, the present invention is a semiconductor arithmetic circuit, comprising a logical circuit group containing a plurality of threshold logical circuits having at least two input terminals, and undergoing a change of state when the sum of or difference between signals inputted into said two input terminals is in excess of a prescribed value, a means for applying a prescribed signal to the first input terminal of said threshold logical circuit, and a logical operation circuit, wherein the output signals of all said threshold logical circuits contained in said logical circuit group are inputted directly or through prescribed number of inverters to said logical operation circuit, and the output signal of said logical operation circuit is fed back directly, or through prescribed number of inverters, to the respective second input terminal of each said threshold logical circuit contained in said logical circuit group.